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| 155 Mbps ATM SAR Controller With ABR Support for PCI-based Networking Applications IDT77252 x x x x x x x x x x x x x x x x x x x x x x x Full-duplex Segmentation and Reassembly (SAR) at 155 Mbps "wire-speed" (310 Mbps aggregate speed) Operates with ATM Networks up to 155.52 Mbps Stand-alone Controller: Embedded Processor not required Performs ATM Layer Protocol Functions Supports AAL5, AAL3/4, AAL0 and Raw Cell Formats Supports Constant Bit Rate (CBR), Variable Bit Rate (VBR), and Unassigned Bit Rate (UBR), and Available Bit Rate (ABR) Service Classes Segments and Reassembles CS-PDUs into Host Memory Up to 16K Open Transmit Connections Up to 16K Simultaneous Receive Connections ABR, VBR, UBR Selectable per VC Time-out Automatic AAL5 Padding Four Buffer Pools for Independent or Chained Reassembly Supports Any Buffer Alignment Condition Free Buffer Queues Mapped Into PCI Memory Space Rx FIFO Size (Configurable to 1024 Kbytes) Configurable Transmit FIFO Depth for Reduced Latency Supports Big and Little Endian Data Transfers Null Cell Disable Option During Transmit NAND Test Mode RM Cell Handling UTOPIA Level 1 Interface to PHY Utility Bus Interface for PHY Management Serial EEPROM Interface x EPROM Interface x PCI 2.1 Compliant x UNI 3.1, TM 4.0 Compliant x Meets PCI Bus Power Management and Interface Specification Revision 1.1 x Pin Compatible with IDT 77211 SAR x Commercial and Industrial Temperature Ranges x 208-Lead PQFP Package (28 x 28mm) x Software Drivers: - SARWIN 2 Demonstration Program - NDIS Driver - Vx Works (3rd party) - Linux (3rd party) The IDT77252 NICStARTM is a member of IDT's family of products for Asynchronous Transfer Mode (ATM) networks. The ABR SAR performs both the ATM Adaptation Layer (AAL) Segmentation and Reassembly (SAR) function and the ATM layer protocol functions. A Network Interface Card (NIC) or internetworking product based on the ABR SAR uses host memory, rather than local memory, to reassemble Convergence Sublayer Protocol Data Units (CS-PDUs) from ATM cell payloads received from the network. When transmitting, as CSPDUs become ready, they are queued in host memory and segmented 16K x 32 to 512K x 32 SRAM PCI BUS 8 EPROM 32 Rx UTOPIA Bus PCI Interface 8 33MHZ 32 IDT77252 155Mbps PCI ATM ABR SAR 155Mbps PHY 2 2 Tx UTOPIA Bus 8 Utility Bus 8 80.0MHZ OSC. EEPROM 4057 drw 01 1 of 17 2001 Integrated Device Technology, Inc. March 26, 2001 DSC 4057/8 IDT77252 by the ABR SAR into ATM cell payloads. From this, the ABR SAR then creates complete 53-byte ATM cells which are sent through the network. The ABR SAR's on-chip PCI bus master interface provides efficient, low latency DMA transfers with the host system, while its UTOPIA interface provides direct connection to PHY components used in 25.6 Mbps to 155 Mbps ATM networks. The IDT77252 is fabricated using state-of-the-art CMOS technology, providing the highest levels of integration, performance and reliability, with the low-power consumption characteristics of CMOS. Transm it C ontrol Tx U topia Interface 8 / T x U topia Bus 32 S R A M IN T E R FA CE / SRAM Bus PCI Bus . 32 / PCI Interface Rx U topia Interface 8 Receive C ontrol 8 / Bus R x U topia / U tility EE PRO M O U T E E P R O M IN 4057 drw 02 Vcc AD(31) AD(30) AD(29) AD(28) AD(27) AD(26) GND GND AD(25) AD(24) C/BE(3) IDSEL AD(23) AD(22) GND GND AD(21) Vcc AD(20) AD(19) AD(18) AD(17) AD(16) GND GND C/BE(2) Vcc FRAME IRDY TRDY DEVSEL STOP GND GND INTA Vcc PERR SERR PAR C/BE(1) AD(15) GND GND AD(14) AD(13) AD(12) AD(11) AD(10) AD(9) AD(8) GND 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 208 2 2 2 2 2 2 2 2 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 000000009999999999888888888877777777776666666666555 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7156 155 Index 154 153 152 151 150 149 148 147 146 145 144 143 142 141 140 139 138 137 136 IDT77252 SAR Controller 135 With ABR Support 134 133 208 Pin PQFP 132 Pinout 131 130 PU-208 129 DUI-208 128 127 126 Refer to PSC-4053 for 125 124 detailed package drawing 123 122 121 120 119 118 117 116 115 114 113 112 111 110 109 108 107 1 1 1 1 1 106 5 5 5 5 5 5 5 6 6 6 6 6 6 6 6 6 6 7 7 7 7 7 7 7 7 7 7 8 8 8 8 8 8 8 8 8 8 9 9 9 9 9 9 9 9 9 9 0 0 0 0 0 105 34567 890 123 456789 012 345 678901234 56789 012345 67890 1234 Vcc GND C/BE(0) AD(7) Vcc AD(6) AD(5) AD(4) GND SR_A17 AD(3) AD(2) AD(1) AD(0) GND SR_A15 SR_WE SR_A13 SR_A8 SR_A9 SR_A11 SR_OE SR_A10 SR_CS SR_A16 GND SR_A14 Vcc SR_A12 SR_A7 SR_A6 SR_A5 SR_A4 SR_A3 SR_A2 SR_A1 SR_A0 SR_A18 GND SR_I/O(0) SR_I/O(1) SR_I/O(2) SR_I/O(3) SR_I/O(4) SR_I/O(5) GND SR_I/O(6) SR_I/O(7) SR_I/O(8) SR_I/O(9) SR_I/O(10) GND GND Vcc REQ GNT CLK RST GND NAND_EN GND GND CLK_OUT Vcc Vcc ADD18_17_EN GND NAND_OUT GND TXPARITY PHY_CLK RXCLK GND RXEMPTY/RxCLAV RXENB RXSOC RXDATA(7) RXDATA(6) RXDATA(5) RXDATA(4) GND RXDATA(3) RXDATA(2) RXDATA(1) RXDATA(0) GND TXCLK TXFULL/TxCLAV TXENB TXSOC GND TXDATA(7) TXDATA(6) VCC TXDATA(5) TXDATA(4) GND TXDATA(3) TXDATA(2) TXDATA(1) TXDATA(0) UTL_CS(1) UTL_CS(0) Vcc GND PHY_INT PHY_RST UTL_ALE UTL_RD UTL_WR GND UTL_AD(7) UTL_AD(6) UTL_AD(5) UTL_AD(4) Vcc UTL_AD(3) GND UTL_AD(2) UTL_AD(1) UTL_AD(0) Vcc SAR_CLK GND EEDO EEDI EESCLK EECS Vcc E_CE SR_I/O(31) SR_I/O(30) SR_I/O(29) GND SR_I/O(28) SR_I/O(27) SR_I/O(26) SR_I/O(25) SR_I/O(24) Vcc SR_I/O(23) GND SR_I/O(22) SR_I/O(21) SR_I/O(20) SR_I/O(19) SR_I/O(18) SR_I/O(17) GND SR_I/O(16) SR_I/O(15) SR_I/O(14) SR_I/O(13) SR_I/O(12) SR_I/O(11) Vcc 4057 drw 03 2 of 17 March 26, 2001 IDT77252 ! 1.228 0.016 (31.2 0.4) 1.10 0.004 (28.0 0.1) 208 157 1 0.02 0.004 (0.5 0.1) Index 156 0.008 0.004 (0.2 0.1) 52 105 53 104 0.133 0.004 (3.37 0.1) 0.013 0.002 (0.33 0.06) 0.024 0.008 (0.6 0.2) 0.063 (1.6) 4057 drw 04 1 2 3 4 5 6 7 8 9 10 11 12 13 VCC AD(31) AD(30) AD(29) AD(28) AD(27) AD(26) GND GND AD(25) AD(24) C/BE(3) IDSEL I I/O I/O I/O I/O I/O I/O I I I/O I/O I/O I power PCI PCI PCI PCI PCI PCI power power PCI PCI PCI PCI address/data line address/data line address/data line address/data line address/data line address/data line address/data line address/data line bus command bus ID select 3 of 17 1.10 0.004 (28.0 0.1) 1.228 0.016 (31.2 0.4) March 26, 2001 IDT77252 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 AD(23) AD(22) GND GND AD(21) VCC AD(20) AD(19) AD(18) AD(17) AD(16) GND GND C/BE(2) VCC Frame IRDY TRDY DEVSEL STOP GND GND INTA VCC PERR SERR PAR C/BE(1) AD(15) GND GND AD(14) AD(13) AD(12) AD(11) AD(10) AD(9) AD(8) GND I/O I/O I I I/O I I/O I/O I/O I/O I/O I I I/O I I/O I/O I/O I/O I/O I I O I I/O O I/O I/O I/O I I I/O I/O I/O I/O I/O I/O I/O I PCI PCI power power PCI power PCI PCI PCI PCI PCI power power PCI power PCI PCI PCI PCI PCI power power PCI power PCI PCI PCI PCI PCI power power PCI PCI PCI PCI PCI PCI PCI power cycle frame initiator ready target ready bus command address/data line address/data line address/data line address/data line address/data line address/data line address/data line address/data line target indicating address decode target requesting master to stop "interrupt" "A" "request" data parity error system error parity (for AD[0:31] and C/BE[0:3]) bus command address/data line address/data line address/data line address/data line address/data line address/data line address/data line address/data line 4 of 17 March 26, 2001 IDT77252 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 VCC GND C/BE(0) AD(7) VCC AD(6) AD(5) AD(4) GND SR_A17 AD(3) AD(2) AD(1) AD(0) GND SR_A15 SR_WE SR_A13 SR_A8 SR_A9 SR_A11 SR_OE SR_A10 SR_CS SR_A16 GND SR_A14 VCC SR_A12 SR_A7 SR_A6 SR_A5 SR_A4 SR_A3 SR_A2 SR_A1 SR_A0 SR_A18 GND I I power power PCI PCI power PCI PCI PCI power SRAM PCI PCI PCI PCI power SRAM SRAM SRAM SRAM SRAM SRAM SRAM SRAM SRAM SRAM power SRAM power SRAM SRAM SRAM SRAM SRAM SRAM SRAM SRAM SRAM SRAM power Address line Address line Address line Address line Address line Address line Address line Address line Address line Address line Address line Address line Write enable Address line Address line Address line Address line Address line bus command I/O I/O I I/O I/O I/O I O I/O I/O I/O I/O I O O O O O O O O O O I O I O O O O O O O O O O I address/data line address/data line address/data line address/data line address/data line address/data line address/data line address/data line Output Enable control Address line Chip Select Address line 5 of 17 March 26, 2001 IDT77252 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 SR_I/O(0) SR_I/O(1) SR_I/O(2) SR_I/O(3) SR_I/O(4) SR_I/O(5) GND SR_I/O(6) SR_I/O(7) SR_I/O(8) SR_I/O(9) I/O I/O I/O I/O I/O I/O I I/O I/O I/O I/O I/O I I I/O I/O I/O I/O I/O I/O I I/O I/O I/O I/O I/O I/O I I/O I I/O I/O I/O I/O I/O I I/O I/O I/O SRAM SRAM SRAM SRAM SRAM SRAM power SRAM SRAM SRAM SRAM SRAM power power SRAM SRAM SRAM SRAM SRAM SRAM power SRAM SRAM SRAM SRAM SRAM SRAM power SRAM power SRAM SRAM SRAM SRAM SRAM power SRAM SRAM SRAM Data input/output line Data input/output line Data input/output line Data input/output line Data input/output line Data input/output line Data input/output line Data input/output line Data input/output line Data input/output line Data input/output line SR_I/O(10) GND VCC SR_I/O(11) SR_I/O(12) SR_I/O(13) SR_I/O(14) SR_I/O(15) SR_I/O(16) GND SR_I/O(17) SR_I/O(18) SR_I/O(19) SR_I/O(20) SR_I/O(21) SR_I/O(22) GND SR_I/O(23) VCC SR_I/O(24) SR_I/O(25) SR_I/O(26) SR_I/O(27) SR_I/O(28) GND SR_I/O(29) SR_I/O(30) SR_1/O(31) Data input/output line Data input/output line Data input/output line Data input/output line Data input/output line Data input/output line Data input/output line Data input/output line Data input/output line Data input/output line Data input/output line Data input/output line Data input/output line Data input/output line Data input/output line Data input/output line Data input/output line Data input/output line Data input/output line Data input/output line Data input/output line 6 of 17 March 26, 2001 IDT77252 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160 161 162 163 164 165 166 167 168 169 E_CE VCC EECS EESCLK EEDI EEDO GND SAR_CLK VCC O I O O I O I I I EPROM power EEPROM EEPROM EEPROM EEPROM power chip select clock Data input Data output EPROM chip select SAR clock input power Utility Utility Utility power Utility power Utility Utility Utility Utility power Utility Utility Utility PHY PHY power power Utility Utility UTOPIA UTOPIA UTOPIA UTOPIA power UTOPIA UTOPIA power UTOPIA UTOPIA transmit data bit 6 transmit data bit 7 transmit data bit 4 transmit data bit 5 chip select (0) chip select (1) transmit data bit 0 transmit data bit 1 transmit data bit 2 transmit data bit 3 write control read control address latch enable rest control interrupt input from PHY address/data bus address/data bus address/data bus address/data bus address/data bus address/data bus address/data bus address/data bus UTL_AD(0) UTL_AD(1) UTL_AD(2) GND UTL_AD(3) VCC UTL_AD(4) UTL_AD(5) UTL_AD(6) UTL_AD(7) GND UTL_WR UTL_RD UTL_ALE PHY_RST PHY_INT GND VCC UTL_CS(0) UTL_CS(1) TxData(0) TxData(1) TxData(2) TxData(3) GND TxData(4) TxData(5) VCC TxData(6) TxData(7) I/O I/O I/O I I/O I I/O I/O I/O I/O I O O O O I I I O O O O O O I O O I O O 7 of 17 March 26, 2001 IDT77252 170 171 172 173 174 175 176 177 178 179 180 181 182 183 184 185 186 187 188 189 190 191 192 193 194 195 196 197 198 199 200 201 202 203 204 205 206 207 208 GND TxSOC TxEnb I O O I O I I I I I I I I I I I O I I O I O I O I I I I O I I I I I I I O I I power UTOPIA UTOPIA UTOPIA UTOPIA power UTOPIA UTOPIA UTOPIA UTOPIA power UTOPIA UTOPIA UTOPIA UTOPIA UTOPIA UTOPIA UTOPIA power UTOPIA UTOPIA UTOPIA power power power power power power power power power power power PCI PCI PCI PCI power power transmit start of cell transmit enable control transmit buffer full transmit data sync clock TxFull/TxCLAV TxCLK GND RxData(0) RxData(1) RxData(2) RxData(3) GND RxData(4) RxData(5) RxData(6) RxData(7) RxSOC RxEnb RxEmpty/RxCLAV GND RxClk PHY_Clk TxParity GND NAND_OUT GND ADD17_18_EN VCC VCC CLK_OUT GND GND NAND_EN GND RST CLK GNT REQ VCC GND receive data bit 0 receive data bit 1 receive data bit 2 receive data bit 3 receive data bit 4 receive data bit 5 receive data bit 6 receive data bit 7 receive start of cell receive enable control receive buffer empty receive data sync clock Transmit sync clock input transmit data parity bit NAND output chain enables or tristates SR_A17 and SR_A18 SAR_Clk divided by 3 NAND input chain system bus reset bus clock bus grant signal from arbiter bus request 8 of 17 March 26, 2001 IDT77252 " #$ $ VCC VIN VOUT Tstg -0.3 VSS - 0.3 VSS - 0.3 -55 6.5 VCC + 0.3 VCC + 0.3 125 V V V Supply Voltage Input Voltage Output Voltage Storage Temperature deg.C %% % %%& ' % VCC VI TA1 TA2 titr titf Supply Voltage Input Voltage Commercial Operating temperature Industrial Operating temperature Input TTL rise time Input TTL fall time 0 0 4.75 5.25 VCC 70 85 2 2 V V deg.C deg.C ns ns -40 -- -- ' SAR_CLK SAR clock input freq. 155Mb/s 25Mb/s 77 25 80 80 40 40 33.3 MHz MHz MHz MHz MHz PHY_CLK PHY clock input freq. 155Mb/s 25Mb/s 19.44 3 0 PCI_CLK PCI clock input freq. 33MHz ' CIN COUT Cbid Cinpci Cclkpci Cidsel Input Capacitance Output Capacitance Bi-Directional Capacitance PCI Bus Input Capacitance PCI Bus Clock Input Capacitance PCI Bus ID Select Input Capacitance except PCI Bus all outputs all bi-directional pins PCI Bus inputs -- -- -- -- -- -- 5 -- -- -- -- 10 12 8 4 6 10 -- -- -- pF pF pF pF pF pF ' % '& ' % Vil Vih Vol Vol Voh Low-level TTL input voltage High-level TTL input voltage Low-level TTL output voltage PCI Bus Low-level TTL output voltage High-level TTL output voltage -- -- -0.7V 2 -- -- 2.4 0.8 -- -- -- -- -- VCC + 0.2V 0.4 0.55 -- V V V V V except PCI Bus PCI Bus voltage -- 9 of 17 March 26, 2001 IDT77252 Iol Ioh Iol Low-level TTL output current: SR_A(18-0) High-level TTL output current: SR_A(18-0) Low-level TTL output current: RxEnb, RxClk, TxSOC, TxData (7-0), TxEnb, TxParity, TxClk, WE#, OE#, CS#, SR_D31-0 High-level TTL output current: RxEnb#, RxClk, TxSoc, TxData7-0, TxEnb#, TxParity, TxClk, SR_WE, SR, OE, SR_CS, SR_I/O(31-0) Low-level TTL output current: UTL_AD(7-0), UTL_RD, UTL_WR, UTL_ALE, UTL_CS0/1, EESCLK, EECS, EEDO, PHY_RST High-level TTL output current: UTL_AD(7-0), UTL_RD, UTL_WR, UTL_ALE, UTL_CS0/1, EESCLK, EECS, EEDO, PHY_RST Input leakage current Dynamic Supply Current VSS + 0.4V 2.4V VSS + 0.4V 12 -4 6 -- -- -- -- -- -- mA mA mA Ioh 2.4V -2 -- -- mA Iol VSS + 0.4V 3 -- -- mA Ioh 2.4V -1 -- -- mA Iil Ityp VSS VIN Vdd -- -1 -- 1 300 -- 250 uA mA '& ' % % Input Pulse Levels Input Rise/Fall Times Input Timing Ref. Level Output Ref. Level AC Test Load 0 to 3.0V 2ns 1.5V 1.5V See Figure Below Table 1 AC Test Conditions 6 5 1.5V 50 I/O Z0 = 50 4 tCD 3 (Typical, ns) 2 1 20 30 50 80 100 Capacitance (pF) 200 4057 drw 05 (() The NAND Chain provides a simple test to verify that all bond wires are installed correctly and that all pads are correctly soldered on a PCB. All signal pads are linked in a NAND chain, which is enabled by asserting a high, or "1", on NAND_EN (pin 201). Asserting a "1" on the other inputs forces NAND_OUT (pin 193) to "1". By successively setting the inputs to "0", starting at CLK_OUT (pin 198) and moving to TXPARITY (pin 191), NAND_OUT will toggle with each change. 1. Apply a "1" to NAND_EN. 2. Set all the I/O's in the chain to "0" and NAND_OUT should be a "1".The connection order of the pins in the chain are shown in the NAND Tree Pin Order table located on the following page. 3. Set CLK_OUT to a "0" and the NAND_OUT should be a "0". 4. Leaving pin 198 at a "1" set RST (pin 203) to "1" and NAND_OUT should be a "1". 5. Repeat for all remaining I/O's in the NAND chain. 10 of 17 March 26, 2001 IDT77252 ! CLK_OUT RST CLK GNT REQ AD[31] AD[30] AD[29] AD[28] AD[27] AD[26] AD[25] AD[24] C/BE[3] IDSEL AD[23] AD[22] AD[21] AD[20] AD[19] AD[18] AD[17] AD[16] C/BE[2] Frame IRDY TRDY DEVSEL STOP INITA PERR SERR PAR C/BE[1] AD[15] AD[14] AD[13] 198 203 204 205 206 2 3 4 5 6 7 10 11 12 13 14 15 18 20 21 22 23 24 27 29 30 31 32 33 36 38 39 40 41 42 45 46 ! AD[12] AD[11] AD[10] AD[9] AD[8] C/BE[0] AD[7] AD[6] AD[5] AD[4] AD[3] AD[2] AD[1] AD[0] SR_WE SR_A[13] SR_A[8] SR_A[9] SR_A[11] SR_OE SR_A[10] SR_CS SR_A[12] SR_A[7] SR_A[6] SR_A[5] SR_A[4] SR_A[3] SR_A[2] SR_A[1] SR_A[0] SR_I/O[00] SR_I/O[01] SR_I/O[02] SR_I/O[03] SR_I/O[04] SR_I/O[05] 47 48 49 50 51 55 56 58 59 60 63 64 65 66 69 70 71 72 73 74 75 76 81 82 83 84 85 86 87 88 89 92 93 94 95 96 97 ! SR_I/O[06] SR_I/O[07] SR_I/O[08] SR_I/O[09] SR_I/O[10] SR_I/O[11] SR_I/O[12] SR_I/O[13] SR_I/O[14] SR_I/O[15] SR_I/O[16] SR_I/O[17] SR_I/O[18] SR_I/O[19] SR_I/O[20] SR_I/O[21] SR_I/O[22] SR_I/O[23] SR_I/O[24] SR_I/O[25] SR_I/O[26] SR_I/O[27] SR_I/O[28] SR_I/O[29] SR_I/O[30] SR_I/O[31] E_CE EECS EESCLK EEDI EEDO SAR_CLK UTL_AD[0] UTL_AD[1] UTL_AD[2] UTL_AD[3] UTL_AD[4] 99 100 101 102 103 106 107 108 109 110 111 113 114 115 116 117 118 120 122 123 124 125 126 128 129 130 131 133 134 135 136 138 140 141 142 144 146 ! UTL_AD[5] UTL_AD[6] UTL_AD[7] UTL_WR UTL_RD UTL_ALE PHY_RST PHY_INT UTL_CS[0] UTL_CS[1] TxData[0] TxData[1] TxData[2] TxData[3] TxData[4] TxData[5] TxData[6] TxData[7] TxSOC TxEnb TxCLAV TxCLK RxData[0] RxData[1] RxData[2] RxData[3] RxData[4] RxData[5] RxData[6] RxData[7] RxSOC RxEnb RxCLAV RxCLK PHY_CLK TxParity 147 148 149 151 152 153 154 155 158 159 160 161 162 163 165 166 168 169 171 172 173 174 176 177 178 179 181 182 183 184 185 186 187 189 190 191 Table 2 NAND Tree Pin Order 11 of 17 March 26, 2001 IDT77252 '*+,% % tval tval(ptp) ton toff tsu tsu(ptp) th trst-pwr trst-clk trst-off thigh tlow 1. 2 2 2 -- 7 10(12) 21 1 100 11 12 -- 28 -- -- -- -- -- 40 -- -- ns ns ns ns ns ns ns ns ns ns ns ns CLK to Output Signal Valid Delay: AD31-0, C/BE3-0, PAR, FRAME, IRDY, DEVSEL, TRDY, STOP, PERR, SERR CLK to Output Signal Valid Delay: REQ Float to Signal Active Delay: AD31-0, C/BE3-0, PAR, FRAME, IRDY, DEVSEL, TRDY, STOP, PERR, SERR Signal Active to Float Delay: AD31-0, C/BE3-0, PAR, FRAME, IRDY, DEVSEL, TRDY, STOP, PERR, SERR Input Setup Time to CLK: AD31-0, C/BE3-0, PAR, FRAME, IRDY, DEVSEL, TRDY, STOP, PERR Input Setup Time to CLK: GNT, (REQ) Input Hold Time from CLK: AD31-0, C/BE3-0, PAR, FRAME, IRDY, DEVSEL, TRDY, STOP, PERR, GNT Reset Active Time After Power Stable Reset Active Time After CLK Stable Reset Active to Output Float Delay: AD31-0, C/BE3-0, PAR, FRAME, IRDY, DEVSEL, TRDY, STOP, PERR, SERR -- Clock high time Clock low time 11n 11n Does not meet PCI Local Bus revision 2.1 timing specification .)& *+/ t1 t2 t3 t4 t5 t6 t7 t8 t9 1. 1 -- 5 15 -- -- 15 -- -- -- -- ns ns ns ns ns ns ns ns ns TxClk, RxClk Delay from PHY_CLK TxData(7-0), TxSOC, TxEnb, TxParity Output Valid from TxClk TxFull/TxCLAV Setup Time to TxClk TxFull/TxCLAV Hold Time from TxClk RxEnb Output Valid from RxClk RxData(7-0), RxSOC Setup Time to RxClk RxData(7-0), RxSOC Hold Time from RxClk RxEmpty/RxCLAV Setup Time to RxClk RxEmpty/RxCLAV Hold Time from TxClk Does not meet UTOPIA 1 timing specification (Af-phy-0017.00) 10 31 1 10 21 10 21 .0' +1 tw1 tw2 tw3 tw4 tw5 tw6 tw7 tw8 tw9 tw10 tw11 UTL_ALE Pulse Width UTL_CS0/1 Output Valid to UTL_ALE falling edge UTL_WR Output Valid from UTL_ALE falling edge UTL_CS0/1 Pulse Width UTL_WR Pulse Width UTL_ALE falling edge to UTL_WR rising edge UTL_AD(7-0) Address Setup Time to UTL_ALE falling edge UTL_AD(7-0) Address Hold Time from UTL_ALE falling edge UTL_AD(7-0) Data Setup Time to UTL_WR rising edge UTL_AD(7-0) Data Hold Time from UTL_WR rising edge UTL_ALE falling edge to UTL_CS0/1 rising edge 25 25 -- 275 175 225 30 10 185 10 250 -- -- 80 -- -- -- -- -- -- -- -- ns ns ns ns ns ns ns ns ns ns ns 12 of 17 March 26, 2001 IDT77252 .%' + tr1 tr2 tr3 tr4 tr5 tr6 tr7 tr8 tr9 tr10 tr11 UTL_ALE Pulse Width UTL_CS0/1 Output Valid to UTL_ALE falling edge UTL_RD Output Valid from UTL_ALE falling edge UTL_CS0/1 Pulse Width UTL_RD Pulse Width UTL_ALE falling edge to UTL_RD rising edge UTL_AD(7-0) Address Setup Time to UTL_ALE falling edge UTL_AD(7-0) Address Hold Time from UTL_ALE falling edge UTL_AD(7-0) Data Setup Time to UTL_CS0/1 rising edge UTL_AD(7-0) Data Hold Time from UTL_CS0/1 rising edge UTL_ALE falling edge to UTL_CS0/1 rising edge 25 25 -- 250 185 250 30 10 80 10 225 -- -- 80 -- -- -- -- -- -- -- -- ns ns ns ns ns ns ns ns ns ns ns #0' +2# t1 t2 t3 t4 t5 t6 SR_A(18-0) Setup Time to SR_WE falling edge SR_CS falling edge to SR_WE falling edge SR_CS pulse width SR_I/O(31-0) Setup Time to SR_WE rising edge SR_I/O(31-0) Hold Time from SR_WE rising edge SR_WE Pulse Width 2 0 -- -- -- -- -- -- ns ns ns ns ns ns 25 6 0 10 #%' +# % % t1 t2 1. -- 25 15 -- ns ns SR_A(18-0) to SR_I/O(31-0) Valid1 SR_OE pulse width SR_I/O (31-0) Setup and Hold times are guaranteed by design when t1 access time is met. 3 &#+4 t1 t2 t3 t4 E_CE Pulse Width 0 75 -- 75 -- -- 70 -- ns ns ns ns SR_I/O(7-0) Hold Time from E_CE rising edge SR_A(18-0) Change to SR_I/O(7-0) Valid SR_A(18-0) Pulse Width 3 &#+5 t1 t2 t3 -- -- -- ns ns ns 10 0 software controlled software controlled software controlled SAR_CLK to Output Signal Valid Delay: EECS, EEDO, EECLK 100 EEDI Input Setup Time to SAR_CLK EEDI Input Hold Time from SAR_CLK 13 of 17 March 26, 2001 IDT77252 tcyc tlow thigh ton PCI_CLK(I) AD31-0(O) tval toff tval (ptp) Add Cmd Data0 Data1 BE3-0 Data2 Data3 C/BE3-0 (O) FRAME(O) IRDY (O) DEVSEL(I) tval toff ton tval tval toff tsu th tsu tsu TRDY(I) REQ (O) ton tval ParA ParD0 ParD1 ParD2 tval(ptp) toff ParD3 tsu(ptp) th 4057 drw 06 PAR(O) GNT(I) Figure 1 The ABR SAR as a PCI Master (illustrates a 4-word write by the ABR SAR to host memory) tsu PCI_CLK (1) th AD31-0(1) C/BE3-0(1) Add Cmd tsu ParA Data0 Data1 Data2 Data3 BE3-0 ParD0 ParD1 ParD2 ParD3 PAR(1) FRAME(1) th th tsu toff th DEVSEL(1) TRDY(O) PERR(O) SERR(O) tval, ton tval, ton toff toff IRDY (1) tval, ton REQ(1) tsu REQ (O) 4057 drw 07 tval Figure 2 The ABR SAR as a PCI Target (illustrates a 4-word write operation by the host device driver to the ABR SAR) 14 of 17 March 26, 2001 IDT77252 t1 PHY_Clk (I) t7 t2 t5 t6 t8 t9 t3 t4 TxClk,RxClk (O) TxData 7-0 TxSOC TxEnb (O) (O) (O) TxParity (O) Txfull/ (I) TxCLAV RxEnb (O) RxData 7-0 (I) RxSOC (I) (I) 5349 drw 08 RxEmpty/ RxCLAV Figure 3 UTOPIA Bus Timing tw11 tw6 tw8 tw3 tw1 tw7 tw2 UTL_ALE(O) tw4 UTL_CS0/1(O) tw5 tw9 UTL_WR(O) UTL_AD(7-0)(I/O) Address (O) (O) Valid Data 4057 drw 09 tw10 Figure 4 Utility Bus Write Cycle tr6 tr1 tr7 tr2 UTL_ALE tr4 UTL_CS0/1 tr5 tr9 UTL_RD UTL_AD7-0 Address (O) (I) Valid Data 4057 drw 10 tr11 tr8 tr3 tr10 Figure 5 Utility Bus Read Cycle 15 of 17 March 26, 2001 IDT77252 t1 SR_A(18-0) t3 t2 SR_CS t6 t4 SR_WE SR_I/O(31-0) 5349 drw 11 t5 Figure 6 SRAM Bus Write Cycle Timing t1 SR_A(18-0) SR_CS t2 SR_OE SR_I/O(31-0) 5349 drw 12 Figure 7 SRAM Bus Read Cycle Timing t3 t4 SR-A (18-0) t2 E_CE Valid Data 4057 drw 13 t1 SR_I/O(7-0) Figure 8 EPROM Timing t1 SAR_CLK EECS EECLK EEDO t2 t3 EEDI 5349 drw 14 Figure 9 EEPROM Timing !% ! % Several software vendors have written IDT77252 software drivers for various operating systems. Please contact your local IDT sales representative for a vendor list, or e-mail atmhelp@idt.com. IDT offers the Sarwin2 demo driver and application suite, which can be used to evaluate the IDT77252 when used with a IDT NIC reference or evaluation adapter. It may also be used as a reference for sample source code when developing a proprietary device driver. Please contact your IDT sales representative or e-mail sarhelp@idt.com to obtain a free CD-ROM. 16 of 17 March 26, 2001 IDT77252 (*' %3 % % NIC Reference and Evaluation adapters are available in several form factors. Bill of Materials (BOM) and schematics are available upon request for each of the NIC adapters. A list of current NIC adapter offerings can be found at www.idt.com. Note: ABR SAR User Manual provides a detailed description of the 77252 operation and registers. % &%* IDT NNNNN Device Type A Power NNN Speed A Package PG PGI DUI Commerical 208-pin Plastic Quad Flatpack Revisions A, B, C, D, E, and F Industrial 208-pin Plastic Quad Flatpack Revisions A, B, C, D, and E Industrial 208-pin Plastic Quad Flatpack Revision F Speed in Mps 155 L Low Power CMOS 77252 155Mbs ATM Segmentation & Reassembly (SAR) Controller for the PCI Local Bus 4057 drw 15 Note: Refer to Errata list for revision history and how to identify revision. Refer to PSC-4053 for detailed package drawing. , ,,! The 77252 PG package is the same package as the 77211 PQF. The 77252 is a direct replacement to the 77211 SAR. To use the 77252 in a 155 Mbps application, a 80 MHz oscillator is required (replace the 50 MHz oscillator used with the 77211). 6 12/01/97: 01/27/98: 05/01/98: 08/11/98: 07/07/99: 09/15/99: 05/02/99: Created new document. Corrected designation of pins 58, 75, and 90 plus made miscellaneous edits. Changed package designation from PQF to PG. Added AC operating conditions. Edited timing diagrams. Corrected descriptions for the following pins (pin 62, 90, 193). Edited package pin out diagram (pin 195). Added Industrial Temp range. Updated software section. Added DUI package information, updated SRAM timing diagrams, updated Utility Bus timing diagrams, updated PCI timing parameters, updated UTOPIA bus timing parameters, updated AC Test Conditions section, updated EEPROM timing diagrams, added NAND Tree description and pin order, updated software section, and added NIC section. Corrected Utility Bus Write, Utility Bus Read, and SRAM Write timing tables. Corrected NAND Tree pin order. Changed from Preliminary to Final data sheet. Added to and rearranged the Features list. 06/22/00: 03/26/01: CORPORATE HEADQUARTERS 2975 Stender Way Santa Clara, CA 95054 for SALES: 800-345-7015 or 408-727-6116 fax: 408-330-1748 www.idt.com for Tech Support: email:sarhelp@idt.com phone: 408-492-8208 The IDT logo is a registered trademark of Integrated Device Technology, Inc. 17 of 17 March 26, 2001 |
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